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Title: Design and Implementation of Efficient Structures for Digital Interpolators
Authors: Ratan, Rajeev
Supervisor: Sharma, Sanjay Kumar
Kohli, Amit Kumar
Keywords: Multirate Signal Processing;Interpolator;Comb Filter;Discrete Time Signal Processing
Issue Date: 8-Jul-2014
Abstract: To fulfill the ever increasing demand of modern electronic devices operating at the different sampling rates, the interest has touched its zenith in the up-sampling based discrete-time signal processing techniques, which can be incorporated by using the efficient digital interpolators. In this research work, the digital interpolators have been implemented efficiently and effectively using the field programmable gate arrays (FPGA) technology. It has also been demonstrated that how performance of the digital interpolators can be improved by using different techniques at the different sampling rates. First, the cascaded integrator comb (CIC) filters with compensation have been proposed using FPGA, and the results have been investigated for the different wireless standards. These results demonstrate that the logic utilization for global system for the mobile communication (GSM), wideband code division multiple access (WCDMA) and worldwide interoperability for the microwave access (WiMax) is 93%, 43% and 51% respectively. The worst case set up time for GSM, WCDMA and WiMax is 20.89 ns, 20.58 ns and 7.50 ns respectively. The worst case clock-to-output time for GSM, WCDMA and WiMax is 6.66 ns, 7.01 ns and 6.79 ns respectively. From the acquired results, it is evident that the CIC filters are efficient for the low-cost applications because the multipliers are not required in its implementation. Due to the absence of multipliers, they exhibit relatively fast response as compared to the conventional technology. However, the pass-band droop present in the CIC filters confine the scope of its practical applications. By employing compensation and multi-stage techniques, the response of CIC filter in the pass-band can be significantly improved, but at the cost of escalated hardware requirement and the computational complexity. For comparison purpose, the CIC filters have been implemented with and without compensation using the FPGA technology. By employing compensation techniques, the response of CIC filter in the pass-band is found to be significantly improved, as the normalized frequency reduces from 0.47 π rad./sample to 0.12 π rad./sample, but at the cost of increased hardware requirement as well as computational burden. The results show that the logic utilization increases to 63% in the case of CIC structures with compensation, while it is 29% for the CIC structures without compensation. The results clearly depict that the proposed digital interpolator structures can be utilized efficiently in the designing and development of the very large scale integration of the modern digital communication systems. However in digital communication systems, the receiver clock may have time-varying offset, which causes inter-symbol interference at the receiver output. One way for compensating this error is to fractionally delay the signal. Therefore to obtain the fractional delay, the Farrow filter structures are extensively explored in the literature and are widely used in practice. Subsequently, the design and analysis of interpolation filters using the Lagrange polynomial based Farrow filtering structures have been carried out. The presented Farrow filter structures have been designed using the Altera DSP builder advanced blockset. It may be observed from the presented results that even though the cubic Lagrange interpolation method provides somewhat less smooth interpolated signal as compared to the quadratic Lagrange interpolation method, but the ripple level reduces from 60 dB to approximately 25 dB, and the computational need also alleviates by 42% in case of multipliers and 18% in case of additions in the cubic Lagrange interpolation approach. Therefore, the Farrow filtering structures for the cubic Lagrange interpolation are found to be optimum for the designing of interpolation filters. However, the simulation results have been compiled for the single-stage interpolation filters. It is noteworthy that the single-stage filters are efficient for the lower order interpolation factors, but for the high rate change (which is required in the modern digital communication systems like WCDMA, WiMax), the single-stage implementation does not provide sufficiently effective response. Therefore for these applications under similar conditions, the multi-stage implementation of the interpolator may be preferred. Further, the efficient implementation of digital interpolation systems for the up-sampling of quadrature amplitude modulation (QAM)/quadrature phase shift keying (QPSK) based multi-stage digital interpolators have also been proposed. Here, the total output power improves from -25.19 dBm to -22.96 dBm, and the peak to average power improves from 6.166 dB to 6.106 dB in the QAM based double-stage interpolation filter. The total output power improves from -28.09 dBm to -25.84 dBm, and the peak to average power improves from 3.181 dB to 3.158 dB in the QPSK based double-stage interpolation filter. But, the multi-stage implementation in turn increases the computational as well as implementation complexity of the overall communication system. However, this complexity can be reduced considerably by using the half-band filters. For channel bandwidths of 20 MHz, 15 MHz, 10 MHz, 7.5 MHz and 5 MHz, the three-stage filtering without the half-band filters can be realized using 100%, 78%, 49%, 30% and 28% of multipliers respectively, which are essential for single-stage filtering. At the same time, the three-stages filtering with the half-band filters can be realized using 100%, 68%, 36%, 21% and 18% of multipliers respectively, which are essential for single-stage filtering. It is evident from the results that the half-band filters are beneficial in the designing of efficient multi-stage digital interpolators from the implementation perspective. In the aforementioned research work, we have explored and simulated the CIC filters with compensation on FPGA, the cubic Lagrange polynomial based Farrow filtering structures, the conventional multi-stage filters and the half-band filters for interpolation in the emerging field of communication engineering for the different wireless standards as well as applications.
Description: Doctor of Philosophy
Appears in Collections:Doctoral Theses@ECED

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