Please use this identifier to cite or link to this item: http://hdl.handle.net/10266/2443
Title: VLSI Implementation of Pipelined FIR filter
Authors: Sharma, Aarti
Supervisor: Kumar, Sanjay
Keywords: FIR Filter, Booth Multiplier, Pipelining
Issue Date: 16-Sep-2013
Abstract: The Finite Impulse Response (FIR) filter are a class of digital filter that have finite impulse response and are extensively used in signal processing and communication system in applications like noise reduction, echo cancellation, image enchancement, speech and waveform synthesis etc. As the complexity of implementation grows with the filter order and the precision of computation, real-time realization of these filters with desired level of accuracy becomes a challenging task. So, the implementation of FIR filters on FPGAs is the need of the day because FPGAs can give enhanced speed and allows reconfigurable architectures for realization of FIR filter. In this dissertation, digital filter has been designed using Kaiser window. This technique is simple conceptually and computationally & it has the adjustable parameter β, which is used to optimize the mainlobe width. The design complexity is much less than that in non-linear optimizations. On the other hand, because in Kaiser window design the stop band attenuation is determined by the window, direct control over the stop-band attenuation can be achieved. The advantages of the Kaiser window compared to the compared to the fixed windows are their near optimality and flexibility. The direct form structure has been used in designing of proposed filter as this approach gives a better performance than common structures in terms of speed of operation, cost and power consumption. The concept of pipelining has been incorporated that results in reducing the delay of the FIR filter, thereby enhancing the speed and reducing the power dissipation as compared to the non-pipelined techniques. The design of non-pipelined and pipelined FIR filter using both the encoding schemes – Radix-4 and Radix-8 has been carried out via Hardware Description Language. Simulation and synthesis for FPGAs are accomplished on XILINX ISE Software (Xilinx ISE 9.2i version) for Spartan 3E series FPGA (Field Programmable Gate Array), target device (XC3S1600E) (Speed Grade-5).
Description: MT, ECED
URI: http://hdl.handle.net/10266/2443
Appears in Collections:Masters Theses@ECED

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