Please use this identifier to cite or link to this item:
|Title:||Analysis and Implementation of DES Using FPGA|
|Abstract:||Secure communication is the prime requirement of every organization. In today’s world the security has became the major aspect of life. It can be achieved by various techniques such as password, cryptography and biometrics. A Field-Programmable Gate Array (FPGA) is a semiconductor device containing programmable logic components called logic blocks, and programmable interconnects. Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or mathematical functions. FPGAs can be used for specific operational behavior, or general purpose CPU functionality depending on the complexity of the device. FPGA applications include DSP applications, imaging, speech recognition, data security, hardware emulation and for many other applications. In the work, the data has been initially converted into their equivalent numbers and are converted to their equivalent binary numbers in order to provide more secured data. Initially, we apply the test vectors to our design through the test bench and then compile, simulate the test bench with the help of model sim software. When the simulation has been completely done then we analyze the result with help of waveform generated by the Model-Sim software. The thesis deals with various parameters such as variable key length, key generation mechanism, etc. used in order to provide optimized results. The classical DES takes 19 nanoseconds of encryption time for an input having data size of 64 bits. The algorithms has been implemented using VHDL, using their standard specifications, and has been implemented on Xilinx Spartan – 3E (XC3S500) FPGA kit. It has been observed while for input data size of 64 bits encryption time of 16 nanoseconds is achieved. There has been improvement of 15.78% in encryption time as compared to the classical DES.|
|Description:||Master of Technology (VLSI Design and CAD)|
|Appears in Collections:||Masters Theses@ECED|
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.