Design and Implementation of High Performance 64-Bit VLIW Microprocessor

Abstract

In the two decades since FPGAs introduced, the way which digital logic is designed and deployed has been radically changed. FPGAs have made possible entirely new types of applications. It is very important to design microprocessor as the part of core of electronic systems, so development and production. On making use of the technology of FPGA to design the microprocessor of logic function, it can quickly realize the function, complete design, cut down development cycle, save cost and quickly realize productions. The subject of the thesis is to design VLIW (is the abbreviation of "Very Long Instruction Word") microprocessor based on FPGA. It designs VLIW microprocessor which contains 64-bit instruction word and 192-bit data, each VLIW instruction word consists of three operations in parallel. The VLIW microprocessor can be designed using a pipeline technology of four stages, and have been implemented by taking advantage of the technology of FPGAs. According to the basic principle of VLIW microprocessor, it is rationally divided into five main modules: Fetch module, Decode module, Register file, Execute module, Writeback module. Each main module is reasonably divided again, and realized the function of every module based on the principle of FPGAs, so as to implement five main modules. At last, the whole function of VLIW microprocessor is completely finished. It completes the data of empty operation, addition, subtraction, multiplication, load and move, read, comparison, XOR, NAND, NOR, NOT, shift left, shift right, barrel shift left, barrel shift right in VLIW microprocessor. It also solves the control competitions and the data competitions in execution module and register file in VLIW microprocessor by the technology of register’s bypass. The concept, trait, principle and structure of the VLIW microprocessor are firstly introduced in the thesis. It presents the pipeline technology, introduces the basic design method and characteristics about FPGAs, elaborates the basic scheme of design a VLIW microprocessor and verifies 16 kinds of operational functions. Finally, it completes the design of VLIW microprocessor. The design is simulated on Modelsim SE and synthesized on Xilinx 13.1. The Thesis pays a significant attention to the analysis of VLIW in terms of pipelining, area so as to maximize throughput.