Please use this identifier to cite or link to this item: http://hdl.handle.net/10266/1629
Title: Design and Implementation of 32-Bit High Speed Booth Wallace MAC Unit
Authors: Kumar, Naveen
Supervisor: Bansal, Manu
Keywords: Multiply and Accumulator;Adder;FPGA;Synop Design Compiler
Issue Date: 7-Sep-2011
Abstract: The addition and multiplication of two binary numbers is the fundamental and most often used arithmetic operation in microprocessors, digital signal processors, and data-processing application-specific integrated circuits. At the heart of data-path and addressing units in turn are arithmetic units, such as comparators, adders, and multipliers. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. Thesis starts with the study of different adder architectures like Carry Chain Adder, Carrylook Ahead Adder, Carry Select Adder and Carry Skip Adder for different operand size like 4-bit,8-bit, 16-bit,32-bit and 64-bit, simulated and synthesized on FPGA using Xilinx ISE and Synopsys Design Compiler. On the basis of their synthesized results, one of the adder which have less delay and minimum area (Carry Select Adder) is chosen. A 32-bit Pipelined Booth Wallace MAC Unit is designed in which the multiplication is done using the Modified Booth Wallace Multiplier and in the final stage addition of multiplier and in accumulator the Carry Select Adder is used and the pipelining is done in the Booth Multiplier and Wallace Tree. To check and verify its functionality on FPGA, LCD and Keyboard interfacing also has been done. This 32-bit pipelined Booth Wallace MAC described in VHDL and synthesized the circuit using 90 nm standard cell library on FPGA and Design Compiler. This MAC has higher speed than conventional or non pipelined Booth Wallace MAC.
Description: M.Tech. (VLSI Design and CAD)
URI: http://hdl.handle.net/10266/1629
Appears in Collections:Masters Theses@ECED

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