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Title: FPGA Implementation of Digital Fir Filter Design
Authors: Kaur, Tanveet
Supervisor: Kumar, Sanjay
Keywords: Kaiser Window Design Technique For Digital Fir Filter Design
Issue Date: 12-Aug-2011
Abstract: The Finite Impulse Response (FIR) filter is a digital filter widely used in Digital Signal Processing applications in various fields like imaging, instrumentation, communications, etc. Programmable digital processors signal (PDSPs) can be used in implementing the FIR filter. However, in realizing a large-order filter many complex computations are needed which affects the performance of the common digital signal processors in terms of speed, cost, flexibility, etc. Field-Programmable gate Array (FPGA) has become an extremely cost-effective means of off-loading computationally intensive digital signal processing algorithms to improve overall system performance. The FIR filter implementation in FPGA, utilizing the dedicated hardware resources can effectively achieve application-specific integrated circuit (ASIC)-like performance while reducing development time cost and risks. In this thesis, digital FIR filter has been designed by using Kaiser windows. This technique is simple conceptually and computationally. The design of the filter is formulated as a problem of optimizing Io(x), which is the modified zeroth-order Bessel function of the first kind. Besides this the adjustable parameter , has been selected so as to optimise the mainlobe width. Design examples have also shown that the design complexity of the Kaiser window approach is much less than that in nonlinear optimizations. On the other hand, because in Kaiser designs the stopband attenuation is determined by the window, direct control over the stopband attenuation can be achieved. The FIR filter is implemented in Spartan-III-xc3s200-4tq144 FPGA and simulated with the help of Xilinx ISE (Integrated Software Environment). Software WEBPACK project navigator 10.1 was used for synthesizing and simulation the code. For an N order filter the number of shift register and adders required is N and the number of multipliers required is M+1. These filters can work in real time.
Description: M.Tech.
Appears in Collections:Masters Theses@ECED

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