Please use this identifier to cite or link to this item: http://hdl.handle.net/10266/1447
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dc.contributor.supervisorAgarwal, Alpana-
dc.contributor.supervisorAgarwal, Nidhi-
dc.contributor.authorSingh, Anil-
dc.date.accessioned2011-07-29T12:22:51Z-
dc.date.available2011-07-29T12:22:51Z-
dc.date.issued2011-07-29T12:22:51Z-
dc.identifier.urihttp://hdl.handle.net/10266/1447-
dc.descriptionM. Tech (VLSI Design and CAD)en
dc.description.abstractThe main objective of this dissertation is to study and design pipelined ADC which offers attractive combination of high-speed, high-accuracy and low power consumption. With the advancement of Deep Sub-micron (DSM) technology, the low power supply became the trend of circuit designing. However, signal dynamic range decreases due to the reduction in the supply voltage which gives challenge to circuit designers to restore the dynamic range along with the reduction of noise and signal distortion. This work is divided in two parts: First, study of Pipelined Analog to Digital Converter to study the accuracy and various errors in pipelined ADC. Second, is its design for accuracy with low power. A resolution of 8-bit and 30 MS/sec sampling rate is chosen targeting the applications in Wireless Local Area Network (WLAN) and Wide Area Network (WAN). The design was simulated in UMC 0.18 μm Mixed Mode CMOS 1P6M process with power supply of 1.8V in Cadence Analog Design environment.en
dc.description.sponsorshipDIT (GOI) through SMDP - VLSI Project (Phase - II) & Electronics & communication Engineeringen
dc.format.extent4045099 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoenen
dc.subjectPipelineden
dc.subjectAnalog to Digital Converter (ADC)en
dc.subjectDeep Sub-micronen
dc.subjectWLANen
dc.subjectWANen
dc.titlePipelined Analog to Digital Converter - Study and Designen
dc.typeThesisen
Appears in Collections:Masters Theses@ECED

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