FPGA Implementation of Booth Wallace Multiplier

Abstract

A fast and energy-efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially to the total power consumption of the system. On VLSI level, the area also becomes quite important as more area means more system cost. Speed is another key parameter while designing a multiplier for a specific application. These three parameters i.e. power, area and speed are always traded off. Speaking of DSP processors, area and speed are the most important factors. But sometimes, increasing speed also increases the power consumption, so there is an upper bound of speed for a given power criteria. Considering the battery operated portable multimedia devices, low power and fast designs of multipliers are more important than area. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. So this thesis work is devoted for the design and comparison of different 8-bit and 16-bit Booth Wallace Tree Multipliers Comparison is based on the synthesis result obtained by synthesizing all multiplier architecture toward FPGA. A method has been proposed in the Booth Wallace tree multiplier to calculate 2’s complement of multiplicand for final Partial Product Row (PPR) if using MBE technique so as to reduce an extra row of carry save adders which reduces area and delay of the multiplier. This method has been used in the design for speed enhancement of our multiplier.

The report throws light on the basic principles and methods of binary multiplication process. The new algorithm which reduces the last negative signal in the partial product row is discussed to develop the new architecture. The simulation and synthesis results show the values of both the multipliers regarding different parameters.