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TIET Digital Repository
TuDR is the digital asset management system which integrates the intellectual output in the form of research articles, PhD Theses, M.Tech/ME Theses. TuDR facilitates the share and exchange of intellectual output of the university.
TIET Digital Repository
Browsing by Author Chatterjee, Arun Kumar
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Showing results 1 to 20 of 33
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Issue Date
Title
Author(s)
23-Sep-2009
Analysis and Design of a DRAM Cell for Low Leakage
Chatterjee, Arun Kumar
;
Singh, Rashmi
24-Sep-2009
Analysis and Design of a DRAM Cell for Low Leakage
Chatterjee, Arun Kumar
;
Singh, Rashmi
23-Sep-2009
Analysis and Design of Cache Memory Cell for Leakage Power Reduction
Chatterjee, Arun Kumar
;
Sachdeva, Rohit
3-Nov-2009
Analysis, Verification and FPGA Implementation of Vedic Multiplier With Bist Capability
Chatterjee, Arun Kumar
;
Kumar, Vinay
18-Aug-2017
Analytical Drain Current Model of Fully Depleted Silicon-On-Insulator MOSFET with Back-Gate Control
Chatterjee, Arun Kumar
;
Gupta, Anjali Kumari
23-Jul-2015
Analytical Modeling of Drain Current in the Subthreshold Region for Double-Gate Junctionless MOSFET
Chatterjee, Arun Kumar
;
Deb Singha, Arindam
18-Aug-2017
Analytical Modeling of Subthreshold Current in Graded-Channel Dual-Material Double-Gate MOSFET
Chatterjee, Arun Kumar
;
Pankaj
Aug-2018
Analytical Modeling of Threshold Voltage and Subthreshold Drain Current for Double-gate Junctionless MOSFET
Chatterjee, Arun Kumar
;
Bharti, Aman
26-Aug-2014
Applications of Capacitance in Monitoring of Microbial Biofilms
Ghosh, Moushumi
;
Chatterjee, Arun Kumar
;
Singh, Pawandeep
23-Jul-2015
Design and Analysis of a Low Power Tri-Gate Trapezoidal Finfet
Chatterjee, Arun Kumar
;
Musalgaonkar, Gaurav
14-Aug-2014
Design And Analysis of Nanocrystal Flash Memory Cell Based on Single Gate and Double Gate Mosfet Strutures
Chatterjee, Arun Kumar
;
Singla, Anurag
18-Oct-2023
Design and Analysis of Structurally Engineered Junctionless Field-Effect-Transistor
Chatterjee, Arun Kumar
;
Pandey, Rishikesh
;
Kumar, Sandeep
3-Aug-2012
Design and Simulation of Low Power and Stable 7T SRAM Cell
Chatterjee, Arun Kumar
;
Puri, Nikhil
25-Nov-2011
DESIGN AND VERIFICATION OF nMOSFET FOR LOW LEAKAGE AT 90nm PROCESS TECHNOLOGY
Chatterjee, Arun Kumar
;
Trivedi, Parul
27-Aug-2013
Design of a high speed and low power sense amplifier
Chatterjee, Arun Kumar
;
Kumar, Sunil
10-Aug-2018
Design of a Low Power 8T SRAM Cell with Improved Stability
Chatterjee, Arun Kumar
;
Sharma, Gaurav
27-Aug-2013
Design of high speed and low power SRAM decoder
Chatterjee, Arun Kumar
;
Jain, Shivkaran
30-Aug-2010
Design of Low Power and High Speed Sense Amplifier
Chatterjee, Arun Kumar
;
Himanshu
3-Aug-2010
Design of Low Power High Performance SOI Dram Cell
Chatterjee, Arun Kumar
;
Harsimranjot
5-Oct-2011
Design of Partially Depleted SOI MOSFET for Low Power Application
Chatterjee, Arun Kumar
;
Agrawal, Shiva