Layer-Aware 3D Partitioning in VLSI Circuit using Cuckoo Search Meta-heuristic - Parashar, Ashwin (My University, 2015)
Three-Dimensional (3D) technology has great potential to improve the performance and ease of heterogeneity of the integrated system design. As the size of circuit increases day-by-day with the demand of more functionality and good performance requirements. To satisfy all these demands Two-Dimensional (2D) system design is not sufficient. This will enforce the researchers for the beginning of 3D-era. 3D Integrated Circuits (ICs) provide an appealing alternative to the 2D ICs. In simple term, stacking of 2D planar circuits form 3D circuit. By using 3D system design technology, one can integrate the several best technologies into the cube for the fulfillment of the requirements of an application. To achieve the high potential of the 3D ICs, it is more important to design strategies in such a way that can handle objectives and the complexness of the 3D design. Partitioning is an initial and crucial phase of physical design cycle for a circuit. In partitioning, the netlist is divided into several parts by satisfying the constraints subjected to the system. But in the 3D partitioning, partitioning of netlist is not only the sufficient step. Although, it is required to assign partitioned blocks to the different layers of the 3D design of the system. Inter-block connections are responsible for the inter-layer communication of the design. These inter-connections are realized by using Through-Silicon-Via (TSV) technology on the circuit board. TSV has great impact on the performance of the circuit due to the reasons that it affects the global wire-length, signal delay of the circuit and many more. A TSV occupy more area as compared to other components of the circuit on die area. This fact cannot be ignored because numbers of TSVs may lead to the larger size of the chip. Hence, optimization of TVS becomes main objective in 3D-partitioning of physical design. In the work, an approach named TPCM (Three-dimensional Partitioner based on Cuckoo Meta-heuristic) based on the Cuckoo Search Meta-heuristic for the partitioning and layer assignment of the netlist in 3D system design, with the satisfaction of constraints like area balancing, inter-tier connections optimization etc is proposed. The proposed TPCM approach is tested against IBM benchmarks and the results are compared with the Meta-Genetic algorithm. The results show better performance of proposed approach for the 3D-partitioning in comparison with Meta-Genetic one.
ME, CSED
Keywords: VLSI, Cuckoo, Meta-heuristic; CSED