Design for Testability – Pattern Generation and Simulation of Complex Circuits - Kaur, Amandeep (My University, 2019)
Even though a circuit is designed error-free, manufactured circuits may not function correctly. Since the manufacturing process is not perfect, some defects such as short-circuits, open-circuits, open interconnections, pin shorts, etc., may be introduced. Points out that the cost of detecting a faulty component increases ten times at each step between prepackage component test and system warranty repair. It is important to identify a faulty component as early in the manufacturing process as possible. Therefore, testing has become a very important aspect of any VLSI manufacturing system. Design for testability presents effective and timely testing of VLSI circuits. BIST architecture is used to test the circuits effectively compared to scan based testing. In built-in self test (BIST), on-chip circuitry is added to generate test vectors or analyze output responses or both.
Keywords: DFT; ATPG; Scan Insertion; Simulation; Pattern Generation