Power Aware Efficient Approximate Multiplier Design with Automated Power Rollup and Indicator - Panda, Shauvik (My University, 2018)
Power is the most valuable design metric in today’s world. The reduction of power will provide competitive edge to any product. Multiplier is a versatile component in digital system and is a part of many error tolerant applications. The approximation in multiplier can enable low power by sacrificing the exact output. Performance parameters can be improved by reducing the exactness in the actual output. But this approximation needs a constant monitoring as it can temper the original functionality. Power management is also important as by doing efficient power management in terms of power aware system, a lot of power can be saved. Now, power estimation is also a big challenge to provide insight to the power projection at different stages of the design. This work revolves around the efficient approximate multiplier in terms of power and speed. Circuit and algorithmic changes in approximate multiplier results into 61.2%, 41.2% and 49.1% power reduction using structures of Ripple Carry Adder (RCA), Carry Select Adder (CSA) and CSA with Binary to Excess 1 Converter (BEC) in comparison to the exact architecture. Speed has been improvised by 10.2%, 33.3% and 34.5%. Multi Vt structure resulted into 29.2%, 19.7% and 22.2% speed improvement for RCA, CSA, and BEC than the standard Vt architecture. Further a Gaussian filter has been implemented using this approximate multiplier. The processed image is having a less than 5% deviation in Peak Signal to Noise Ratio (PSNR) value than the exact multiplier.
M.Tech THESIS (VLSI Design)
Keywords: Approximate circuit; Low Power; Power Indicator; Power Template; Low Error; High Speed.; Multiplier; Multi Vt; UPF