Performance and Analysis of Hybrid Cu/CNT as VLSI Interconnect - Bharti, Ankush (My University, 2015)
As technology scaled down, interconnects delay dominates the gate delay in VLSI circuits. Scaling in device size leads to increase in device density and the more length of interconnects are required to connect these devices. Scaling in technology also leads to decrease in interconnect dimension. Copper is currently used as interconnect material. When dimension of interconnect become equal to mean free path of electron of copper interconnect then effect like electro-migration, grain boundary scattering, surface scattering increase the resistivity of copper significantly. Therefore copper cannot be used in future for high speed integrated circuit as interconnect material. Replacement for copper interconnect with new interconnect material is needed in future. Hybrid Cu/CNT can be promising candidate for future high speed VLSI circuits. The Hybrid Cu/CNT consist of mixture of copper and carbon nanotube. The ground to interconnect capacitance is large in CNT interconnect as compare to ground capacitance in copper interconnects. By covering the copper layer around the CNT results in decrease in capacitance of Hybrid Cu/CNT interconnect. This decrease in capacitance results in improve in delay performance of hybrid Cu/CNT based interconnect. Hybrid Cu/CNT has high electrical conductivity, thermal conductivity, and good mechanical strength. In this dissertation, impedance parameter of Hybrid Cu/SWCNT as a VLSI interconnect has been calculated and results are compared with copper interconnects at 32nm, 22nm and 16nm technology nodes for global interconnects length. The effects of interconnect length on propagation delay is analyzed and compared with copper interconnect. It is revealed from result that Hybrid Copper/CNT has improvement in delay in comparison to copper in deep sub-micron technology for global length of interconnect.
ME, ECED
Keywords: SWCNT; Hybrid Interconnect; Delay; Power; ECED