Test Optimization of Core based SOCs Using Various Heuristic Algorithms - Dewan, Naveen (My University, 2015)
The advancement in design methodologies and semiconductor process technologies has led to the development of systems with excessive functionality implemented on a single die, called system-on-chip. A set of pre-designed and pre-verified design modules in the form of soft, hard or firm cores brought from vendors are integrated into a system using user-defined logic (UDL) and interconnects. Complex systems can be implemented having digital, analog and mixed signal components. The urgent time to market requirement poses many challenges for the design and test engineers. Testing cost has made IC testing more difficult. ITRS semiconductor roadmap represents that there will be a need of hundred of processors for the future generation of SOC designs which will further increase the test cost. Testing of SOC is costly due to large data volume introduced due to increase in the integration and interconnection intricacies, huge power dissipation during test, expensive test generation procedures, heterogeneous mix of cores and their long test application times. Many techniques have been proposed to reduce the cost by test scheduling, reducing test data volume and optimizing test design mechanisms. Test generation can either be done off-chip by employing ATPG (Automatic test pattern generation) algorithms running on expensive automatic test equipments or on-chip using a built-in hardware called BIST (Built In Self Test). BIST offers the benefits in case if on-chip the availability of TAM is less. However BIST ready cores are not always available, also the multi site testing of SOC for test time reduction makes the ATE more promising. TAM optimization and test scheduling have been the integral part of the research and test optimization for past three decades. Test scheduling is proved to be an NP-hard problem. This paper proposes a greedy algorithm based approach and enhanced ant colony optimization algorithm based approach for test scheduling to reduce the test time subject to test power, bandwidth and hierarchical constraint. We can reduce the problem into a rectangle packing problem. Experimental results for ITC’02 benchmark circuits show the optimal results achieved. The proposed schemes are applied on three benchmark circuits from Duke University and Philips and they are d695, p22810, p93791.
M.Tech. (VLSI Design)
Keywords: SOC Test , test scheduling design; test optimization; ECED