Design of Low Power CMOS Cell Structures Based on Subthreshold Conduction Principle - Sharma, Vishal (My University, 2010)
While performance and area remain to be two major design goals, power consumption has become a critical concern in today’s VLSI system design. Also the battery operated devices demand to reduce the power to increase the life of devices. Digital circuits operating in the subthreshold region of the transistor are being used as an ideal option for ultra low power complementary metal oxide semiconductor (CMOS) design. But in subthreshold circuit design the performance of the circuit degrades significantly. Hence the use of subthreshold circuit designing in fast and energy efficient circuits is always needed, in electronics industry especially in DSP, image processing and arithmetic units in microprocessors, where the low power is the primary concern and the delay can be tolerated. The main aim of this thesis work is to understand the viability of subthreshold circuit designing to design low power circuits in VLSI. So different CMOS cell structures are designed operating in subthreshold conduction region and also a methodology to identify the minimum energy point, frequency range and operating voltage for CMOS standard cells is defined. The similar CMOS cell structures are also designed operating in superthreshold conduction region. Power of these structures are then compared to understand the usefulness of subthreshold circuit designing for low power VLSI design. All these circuits were designed in Mentor Graphics IC Design Architect using standard TSMC 0.18 μm technology, laid out in Mentor Graphics IC Station. All the circuit simulations has been done using various schematics of the structures and post-layout simulations are also being done after they all have been laid-out by considering all the basic design rules and by running the LVS program. Finally, the analysis of the average dynamic power dissipation with respect to the frequency and the supply voltage was done to show the amount of power dissipated by the circuits operating in subthreshold conduction region and superthreshold conduction region. By the analysis, it was seen that the power dissipation in the circuits operating in subthreshold conduction region was in the range of picowatt while the power dissipation in the circuits operating in subthreshold conduction region was in the range of microwatt.
M.Tech. (VLSI Design and CAD)
Keywords: CMOS, Subthreshold Conduction, Low Power CMOS Design