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|Title:||Scalable and Low Overhead Watermarking Based Integrated Authentication and Encryption Scheme for Wireless Sensor Networks|
|Keywords:||Wireless Sensor Networks;Watermarking;Data Authentication;Node Authentication|
|Abstract:||Numerous nodes that form a part of a Wireless Sensor Network (WSN) are usually spread across and deployed in unguarded environments making them vulnerable to plenty of attacks by adversaries. Resource constrained environments in which the complex nexus of nodes is placed pose tough trade-offs in bestowing security solutions that are robust and at the same time lightweight in nature. This thesis proposes a Scalable and Low overhead Watermarking based Integrated Authentication and Encryption (SLoWIAE) scheme for WSNs. It is a novel idea of a scalable watermarking based solution promising amalgamated advantages offered by both encryption as well as authentication schemes in WSNs but at much lower costs. Unlike various cryptographic schemes, the proposed scheme does not require encryption-decryption key(s) to be exchanged prior to the communication. SLoWIAE ensures non-repudiation, confidentiality and protection against eavesdropping in addition to node and data authentication. Strength of the scheme lies in the geographical credentials of the node, temporal credentials of the message and the raw information captured by the sensor node. Dependence of proposed scheme on the information in raw form makes it highly secure. It resorts to the use of simple operations such as shift, insert, extract and ex-or that make it lightweight. Analytical parameters used to check the robustness of the scheme are cracking probability and communication overhead. The results obtained are compared with a recently published scheme and show that SLoWIAE is found to be more efficient by a factor of ~1032 with an infinitesimal increase of communication overhead. This makes SLoWIAE an ideal candidate to be employed as a security solution in resource constrained environments such as WSNs. The proposed scheme is simulated using Xilinx ISE design suite and implemented on Basys-3 Artix-7 FPGA. It has also been implemented on Cadence RTL Encounter to calculate its area and power consumption.|
|Description:||Master of Technology -ECE|
|Appears in Collections:||Masters Theses@ECED|
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