Thapar University Digital Repository
http://tudr.thapar.edu:8080/jspui
The DSpace digital repository system captures, stores, indexes, preserves, and distributes digital research material.Sat, 18 Nov 2017 17:59:44 GMT2017-11-18T17:59:44ZThapar University 31st Convocation
http://hdl.handle.net/10266/4972
Title: Thapar University 31st ConvocationSat, 04 Nov 2017 00:00:00 GMThttp://hdl.handle.net/10266/49722017-11-04T00:00:00ZTotal Synthesis of Biologically Active Natural Products Involving Asymmetric Induction Using Chiral Catalysis
http://hdl.handle.net/10266/4971
Title: Total Synthesis of Biologically Active Natural Products Involving Asymmetric Induction Using Chiral Catalysis
Authors: Suraksha; Pandey, Satyendra Kumar (Guide)
Abstract: We have described herein enantioselective approaches for the synthesis of (+)-serinolamide A, (-)-haliclamide, (+)-petromyroxol, (+)-phomonol, (+)-epi-muricatacin and (-)-6-acetoxy-hexadecanolide employed Trost’s DYKAT, MacMillan organocatalyzed aldol reaction, Sharpless AD and Jacobsen’s HKR reactions as key steps.. The merits of these synthetic approaches are high enantio- and diastereoselectivity with high yielding reaction steps. All the new compounds were characterized by 1H-NMR, 13C NMR, HRMS, %ee by chiral HPLC and [α]D25 for all new chiral compounds.Thu, 02 Nov 2017 00:00:00 GMThttp://hdl.handle.net/10266/49712017-11-02T00:00:00ZSymmetry Analysis of Nonlinear Fractional Partial Differential Equations
http://hdl.handle.net/10266/4970
Title: Symmetry Analysis of Nonlinear Fractional Partial Differential Equations
Authors: Singla, Komal; Gupta, Rajesh Kumar (Guide)
Abstract: Fractional calculus is a branch of mathematics that deals with real number
or complex number powers of the differential operator and integral operator. Although
the idea of fractional calculus was born more than 300 years ago, serious efforts have
been dedicated to its study recently. Fractional differential equations (FDEs) are gen-
eralization of the differential equations of integer order, studied through the theory of
fractional calculus. Lie symmetry method is a powerful technique for solving integer
order differential equations. In this thesis, its various extensions are proposed for the
symmetry analysis of nonlinear systems of FDEs. The aim of this thesis is to extend
the symmetry approach in order to apply them to a wider class of FDEs including time
fractional nonlinear systems, space-time fractional nonlinear systems, higher dimensional
nonlinear systems, and variable coefficient nonlinear systems.
The thesis consists of six chapters comprising various novel extensions and appli-
cations of the symmetry method.
Chapter 1
provides the history of fractional calculus,
basic definitions, and properties of the Riemann-Liouville fractional operators used in
this study. The main features, background and methodology of the Lie classical method
by Sophus Lie are also discussed in the introductory chapter.
Chapter 2
deals with the extension of Lie symmetry method for studying
i
ii
time fractional systems of partial differential equations (PDEs). The prolongation for-
mulae given in a recent paper [86] for symmetry analysis of time fractional systems are
proved incomplete and the correct formulae are suggested in this chapter. The prolon-
gation operators are derived for time fractional systems having two independent and an
arbitrary number of dependent variables. Also, the technique to investigate nonlinear
self-adjointness and conservation laws is extended for time fractional systems of PDEs.
The proposed methods are applied for the symmetry analysis and derivation of conserved
vectors of five time fractional nonlinear systems of PDEs including Ito system, Burg-
ers system, coupled KdV system, Hirota-Satsuma coupled KdV system, coupled Hirota
equations. As a result, these systems are reduced into fractional nonlinear systems of
ordinary differential equations (ODEs).
Chapter 3
is devoted to extending the Lie group method and Noether operators
for computing Lie symmetries and conserved vectors of space-time fractional PDEs. The
complete Lie group classification is performed and concept of nonlinear self-adjointness
is extended for space-time fractional PDEs. Two space-time fractional nonlinear PDEs
namely Gilson-Pickering equation and generalized KdV equation are studied for their Lie
symmetries resulting in their reductions into fractional nonlinear ODEs in the Erd ́
e
lyi-
Kober operators. In addition, the conservation laws for both the fractional partial differ-
ential equations (FPDEs) are obtained successfully.
Chapter 4
is concerned with the investigation of space-time fractional nonlinear
systems of PDEs for their Lie symmetry analysis. For this purpose, the symmetry method
is proposed for space-time fractional systems of PDEs by derivation of the required pro-
longations. Using the extended prolongation operators, the group infinitesimals for five
space-time fractional nonlinear systems are successfully calculated. The resulting group
iii
invariant solutions are used to obtain their symmetry reductions into nonlinear systems
of fractional ordinary differential equations (FODEs). The discussed fractional nonlinear
systems of PDEs are as follows: space-time fractional Ito system, space-time fractional
coupled Burgers equations, space-time fractional coupled KdV system, space-time frac-
tional Hirota-Satsuma coupled KdV system, space-time fractional coupled Hirota equa-
tions.
In
chapter 5
, a generalized symmetry approach is proposed for systems of
FDEs having an arbitrary number of independent as well as dependent variables. The
derivation of the prolongation operators is discussed for generalized fractional order sys-
tems. The symmetry analysis of higher dimensional systems can be discussed using the
suggested approach. The efficiency of the presented symmetry method is proved by
its application to five higher dimensional nonlinear systems namely (2+1)-dimensional
asymmetric Nizhnik-Novikov-Veselov (ANNV) system, (3+1)-dimensional Burgers sys-
tem, (3+1)-dimensional Navier-Stokes system, (3+1)-dimensional fractional incompress-
ible non-hydrostatic Boussinesq system, fractional (3+1)-dimensional incompressible non-
hydrostatic Boussinesq system with viscosity. Their symmetries and symmetry reductions
into lower dimensional nonlinear fractional order systems are deduced in terms of ex-
tended Erd ́
e
lyi-Kober fractional operators systematically.
In
chapter 6
, certain variable coefficient fractional nonlinear PDEs are inves-
tigated using the Lie group analysis. The complete group classification of fractional
nonlinear variable coefficient PDEs is demonstrated for some single time fractional PDEs
as well as systems of time fractional PDEs with variable coefficients. The studied variable
coefficient fractional nonlinear PDEs include KdV-Burger-Kuramoto equation and gen-
eralized seventh order KdV equation. The considered time fractional nonlinear systems
of PDEs with variable coefficients are coupled Boussinesq system, coupled KdV system
and Hirota-Satsuma coupled KdV system. After computing their group infinitesimals,
the optimal sets of inequivalent one dimensional subalgebras are calculated. Finally, for
each component of the optimal set, the similarity reductions of the considered variable coefficient fractional PDEs are obtained successfully.Thu, 02 Nov 2017 00:00:00 GMThttp://hdl.handle.net/10266/49702017-11-02T00:00:00ZEfficient Test Solutions for System on Chip
http://hdl.handle.net/10266/4969
Title: Efficient Test Solutions for System on Chip
Authors: Vohra, Harpreet; Sengupta, Indranil (Guide); Dhiman, Amardeep (Guide)
Abstract: To cope up with the ever growing demands of the market, more and more number of components are being integrated on a single chip. Realization of complete system comprising of heterogeneous mix of digital and analog logic blocks on a common platform has become feasible owing to the advancements in the design and fabrication techniques. Embedded core based integrated design style has proven to be an effective solution for curtailing the production time and needed design effort for creation of such systems. It involves integration of pre- designed and pre- verified IP cores on a single silicon platform to constitute a system on chip or the so called SoC. Such IP cores can be provided either by the same or some third party design houses in hard, soft or firm information formats.
Advancements in the semiconductor manufacturing technology have led to the development of 3D structures wherein multiple dies are stacked together in vertical dimension. Such structures offer advantages of much higher complexity, lower footprint, lower average power and increased performance. The interconnections between the various dies are provided using low capacity, high density conducting nails called through silicon vias (TSV). Based on the circuit partitioning, 3D SoCs can be categorized as fine grain partitioned SoCs or coarse grain partitioned SoCs. In fine grain partitioned SoC design style, the various core elements may be distributed over multiple dies while in coarse grain, the cores are still 2D but the entire system can be spread over different dies. The necessary interconnections for functional access, power distribution etc. is made possible by using the through silicon vias. Another technological advancement that has taken place in semiconductor industry is the introduction of on chip network as an alternative for bus based interconnects. Being free from different parasitic effects, it offers the advantages of high performance, efficient utilization of bandwidth, low latency, increased throughput, low power dissipation etc. However, such high end design and manufacturing technologies have brought in new design and test challenges.
Manufacturing of billions of components at deep sub-micron level is prone to numerous defects associated with imperfect resolution, misalignment, occurrence of shorts, bridging etc. Such defects can lead to faults which may further degrade the functionality and performance of the systems. To test all the components, they need to be accessed using various input pins and fed with appropriate test patterns. The quality of the systems can be decided by comparing the pre-saved desired outputs with the response of the system to the test patterns which are specifically designed to test the various faults. Increasing level of integration has led to multifold increase in the amount of possible defects which further increases the test data volume. Generation or storage of such a huge test data increases the test cost. Meanwhile, it also increases the time needed to transport the test data between its source and the SoC periphery. Increase in the difference between the on chip components and SoC pins has led to the controllability and observability issues for individual test points.Likewise, other challenges faced by test engineers include: increasing test power, limited test bandwidth, heterogeneous mix of logic styles, increasing on-chip frequency etc. which are making the entire test process a tedious task. To efficiently address the problem of testability of such systems, modular test approach has proven to be a promising solution. It comprises of test infrastructure consisting of test wrappers and test access mechanism which help in providing the necessary isolation and application of test data to the circuit under test. The test solution so developed needs to be optimized to save the test cost. Test time being an integral component of the overall test cost can be reduced by concurrently testing multiple cores. Meanwhile, it is important that the test schedule should not violate the various constraints imposed by test power, test bandwidth, precedence, hierarchical status of the cores etc. The problem of test architecture development for 2D SoCs need to be adapted for 3D SoCs to address the constraint set by maximum number of TSVs available for test purpose. The main objective of the proposed research work has been to develop an efficient test solution for the system on chip. The key contributions include the development of new test data volume minimization techniques and efficient test architecture for 3D SoCs.
This thesis describes five test data compression scheme namely, 10 Coded run length based encoding, Selective Count Compatible Run length encoding, Hierarchical Block Merging based Run length encoding, Optimal Selective Count Compatible Run Length Encoding and Adaptive Block Merging Based Run Length Encoding. All the techniques attempt to improvise over the previously proposed test data compression techniques so as to increase the achievable compression efficiency and reduce the test application time. The minimization of test data is done by employing encoding schemes that merges the test data at block and intra block levels. Existence of compatibility and other properties among the test data blocks are utilized to develop the suitable codewords which can replace the long sequence of test bits. Such schemes reduce the needed ATE memory and test application time.
A test wrapper optimization technique for fine grain partitioned 3DSoC is presented that reduces the test time by appropriately balancing the wrapper chains. Insertion of the various functional elements is done such that the cumulative TSV requirement of all the wrapper chains does not exceed the maximum TSV limit. An efficient test solution for coarse grain partitioned 3D SoC is also presented that reduces the test cost by successively optimizing the test architecture at die levels.
To show the effectiveness, the proposed techniques have been applied to different ISCAS’89 and ITC’02 benchmark circuits. The results so obtained are compared with other previously proposed techniques. Various metrics used to gauge the competence of the test compression techniques include the test compression efficiency, decoder area, test application time and test power. Similarly, the test lengths of the complete SoCs are used to show the effectiveness of the test architectures.Thu, 02 Nov 2017 00:00:00 GMThttp://hdl.handle.net/10266/49692017-11-02T00:00:00Z